| 1. | Dual port memory
双端口记忆器 |
| 2. | Through pci interface and dual port sram , host accessed data from the card
数据采集卡采用pci局部总线接口，通过双端口ram进行数据传输。 |
| 3. | 2 , using dual port ram idt7208 to develop data acquisition board based on pc104 isa bus
2 、利用双端口ram7208开发基于pc104isa总线的数据采集卡。 |
| 4. | This text has recommended the concrete actualized of the software and the hardware composed of an aduc812 , a dual port ram , the cpld and the pci9052 data collecting system in detail
同时，本文详细地介绍了包括aduc812 、双口ram 、 cpld 、 pci9052的数据采集系统软硬件的具体实现。 |
| 5. | A transpose memory is disclosed which has four dual port memories , a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories
一个转置记忆体包含四个双埠记忆体，一个第一个计数器来用将元素写入双埠记忆体，和一个第二个计数器用来从双埠记忆体读出元素。 |
| 6. | If the received matrix is to be outputted to the first type of transform circuit , the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element
假使接收的矩阵将被输出至第一型式转换电路，那麽第一个计数器将收到的每一个矩阵元素写入对应到某一矩阵四分之一象限的特定之记忆体。 |
| 7. | If the received matrix is to be outputted to the second type of transform circuit , the first counter writes each matrix element in a particular dual port memory assigned to the " evenness " or " oddness " ( i . e . , divisibleness by two ) of the row and column of the matrix element
假使接收的矩阵将输出至第二型式转换电路，那麽第一个计数器将收到的矩阵元素写入对应到矩阵单数或双数之栏与行的特定之双埠记忆体。 |
| 8. | I have compared the advantages and disadvantages of these two kinds of schemes , and have confirmed with the data collecting system scheme including an aduc812 , a dual port ram and the pci9052 according to the actual conditions of the teaching and research room
比较了这两种方案的优缺点，并且根据教研室的实际情况确定了以aduc812 、双口ram 、 pci9052构成的数据采集系统方案。列举了目前比较流行的几种pci接口方法，并确定pci9052为系统的pci接口芯片。 |
| 9. | I have proposed two kinds of systematic schemes of interface : one is composed of a high - speed and high - accuracy a / d transition chip , a high - performance dsp chip and the pci bus interface ; the other is composed of a high speed and high - accuracy a / d transition chip , a mcu , a dual port ram and the pci bus interface
提出了由高速高精度a / d转换芯片、高性能dsp芯片、 pci总线接口组成和由高速高精度a / d转换芯片、 mcu 、双口ram 、 pci总线接口组成的两种系统方案。 |
| 10. | This article proposes a primary project of open programmable controller which uses dsp as its controlling core and is aided with cpld , and designs parts of controller involving interpolation and speed detecting . the project using dsp as central processing chip and aided with cpld to communicate with pc and dual port ram as interfaces to peripheral equipments makes full use of advantages of hardware and software . it is also very helpful in machining performance and make the whole system have high real - time ability , less components , compact structure and high anti _ jamming ability . proposing a full numerical speed - detecting system project
本文提出了一种以数字信号处理器( dsp )为控制核心，辅以大规模可编程逻辑器件( cpld )的开放式可编程运动控制器的初步设计方案，并对其中的插补和速度检测部分进行了系统的设计：提出了以dsp (数字信号处理器)为核心处理芯片，辅以cpld和双端口ram实现外围接口与上位机的通讯的设计方案，充分利用了软硬件的优势，对于提高系统的工作性能有极大帮助，使整个系统实时性高，组成元件少，结构紧凑，可靠性高，抗干扰能力强。 |
