| 1. | Also show that this algorithm excels previous iddt atpg algorithm
除了上面这些理论工作之外，结合实际应用，对排序算法进行了研究。 |
| 2. | It is able to combine several parallel strategies quickly and parallelize newest tg and fs algorithms
较之紧耦合串行atpg系统的并行化具有独特的优势。 |
| 3. | At present , the portability of atpg algorithm is the key of blocking its commercialization
目前，制约并行atpg算法实用化的关键原因是算法的可移植性。 |
| 4. | This dissertation designs a data structure , etbl , for rtl circuits for vlsi atpg
本文根据超大规模集成电路自动测试产生要求，设计了rtl电路的数据结构etbl 。 |
| 5. | Finally , we analyse the performance of loosely coupled mode parallel atpg algorithms
国防科学技术大学研究生院学位论文最后，我们对松耦合模式的并行atpg算法进行了性能分析。 |
| 6. | The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究内容正是面向非扫描同步时序电路的并行atpg算法。 |
| 7. | All the theoretical work is applied to 1c design and test applications with some examples . iddt atpg of genetic algorithm based on boolean process
作为布尔过程论的一个应用，针对动态电流测试，提出了动态电流测试的遗传算法测试方法。 |
| 8. | This dissertation focuses on automatic test generation ( atpg ) algorithms for very large - scale integrated circuits at register - transfer - level ( rtl )
本文主要是对大规模、超大规模集成电路寄存器传输级（ rtl ）的自动测试产生算法进行研究。 |
| 9. | An automatic test pattern generation ( atpg ) algorithm for deliberately selected delay faults is presented to cope with the crosstalk - induced delay effects on longer paths
由于电路中较长的通路具有较短的松弛时间，因此容易因为串扰问题产生时延故障。 |
| 10. | At last , the paper involves the flow and related data of logic simulation , logic synthesis and test vector in the risc cpu
论文最后给出了64位vegacpu的asic逻辑仿真文件和仿真波形，逻辑综合策略、综合脚本和综合结果，以及vegacpu基于atpg的测试向量设计流程和相关数据。 |
