| 1. | Morphology of low temperature buffer layers and its influence on inp epilayer growth
低温缓冲层的表面形貌及对其外延层生长的影响 |
| 2. | The results indicated that dmzn flow rate predominately controlled the growth rate of znse epilayer in this work
研究发现实验中znse薄膜生长速率主要受dmzn流量控制。 |
| 3. | B ) sbd was made using the si epilayer as the active layer , qualified with a set of device technology
B )在薄硅外延片的生长基础上，探索制作肖特基二极管的相关工艺，研制高频sbd原型器件。 |
| 4. | With optimized buffer layer growth parameters , gan epilayer with improved quality has been grown , whose fwhm of ( 0002 ) plane dc - xrd rocking curve is 6 arcmin
以优化的缓冲层生长条件得到质量有明显改善的gan外延层， gan薄膜的( 0002 )面双晶dc - xrd扫描的半高宽为6arcmin 。 |
| 5. | By means of quantitative analysis , we accessed growth rate and film thickness of gan epilayer , and even determined in real time the thickness of buffer layer from in situ measurements of normal incidence reflectance
通过对在位监测曲线的分析，确定gan生长速率以及外延层的厚度，并利用监测曲线实时标定缓冲层的厚度。 |
| 6. | Based on the requirement of the device , we grow the films of silicon of high quality . the thickness of the epilayer is from 0 . 4 u m tol p m , the doping concentration can be controlled conveniently
然后，根据器件的要求，利用uhv cvd技术，生长出优质薄硅外延片，其厚度在0 . 4 m 1 m ，掺杂浓度可任意调节，晶体质量良好。 |
| 7. | In order to deal with large mismatch ( 14 . 6 % at room temperature ) between gaas and insb , a insb buffer layer was deposited firstly at low temperature 350 , followed by a insb epilayer being deposited at higher temperature 440
为了克服insb与gaas间14 . 6 %的晶格失配度,实验设计先低温生长一定厚度的insb缓冲层,随后升温生长insb外延层。 |
| 8. | Firstly we analyze the requirement of sbd of high frequency for the doping concentration and thickness of the epilayer , for the structure parameter of the device . we design the optimum device parameter based on this . 2
首先，从理论上分析出高频肖特基二极管对材料的外延层厚度掺杂浓度的要求，以及其它的器件结构参数要求，以此为依据，设计出最佳的器件参数。 |
| 9. | It also put forward that how to select appropriate epilayer doping concentration and thickness , pn junction depth and jte technology to increase the breakdown voltage of 4h - sic mps . a power dissipation model of 4h - sic mps was established
通过对4h - sicmps击穿特性的二维模拟，提出如何选择合适的pn结深度、外延层掺杂浓度和厚度以及如何运用jte终端技术来提高击穿电压。 |
| 10. | No high - temperature pre - heat - treatment of the si substrate was used to obtain epilayers . the zns epilayer quality was improved with decreasing the substrate temperature . the small x - ray diffraction fwhm was obtained at 300 , which implied that the zns epilayers had higher quality
随着生长温度的降低， zns单晶薄膜质量提高，由在300时得到较小x -射线衍射fwhm的结果表明获得了结晶质量较高的zns单晶薄膜。 |
