| 1. | The flow of post - sim with synopsys nanosim amp; star - rcxt
的晶体管级后仿真流程 |
| 2. | 2 . timing setup : load sdc ( synopsys design constraint ) file . define timing analysis options
2 .在时序设置阶段,加入了时序约束,使整个设计在时序启动下完成。 |
| 3. | Synopsys ' s vera is one of the most modern languages designed specially for making testbenches
其中， synopsys公司的vera语言是专用于设计测试平台的现代语言之一。 |
| 4. | After a brief description of asic design flow adopted by pci target secure chip , the thesis make great emphasis on various methods and skills used in physical design and verification with apollo ii from synopsys
物理级设计：在对pci安全芯片所采用的的asic设计流程简单介绍后，文章重点论述了基于apollo的物理设计和验证方法和技巧。 |
| 5. | After evaluating synopsys ' s formality , the paper construes the flow and practical experiences in video post - process chip , and comes to the conclusion that static verification really works
在简单评价了synopsys公司的商用软件formality之后，重点分析了在视频后处理芯片项目中formality的应用流程和实际工作经验，证明形式验证的重要作用。 |
| 6. | The test bench program is a virtual pci system , which comprise the microblaze model established from xilinx edk and also the pci / pci - x model from synopsys company . function level or gate level simulation can be done on this test bench
测试平台中,利用xilinxedk生成的microbalze处理器仿真模型,以及synopsyspci / pci - xflexmodels模型组建了一个虚拟的pci系统,可进行门级和行为级的仿真。 |
| 7. | At last , we compile the design with synopsys design compiler in 0 . 25wn cmos technology . the synthesis information about area , power and time shows that this method has the advantage of fitting special architecture into algorithms easily
最后用0 . 25 mcmos工艺在eda工具上实现，综合结果表明：基于ip核的软硬件协同设计方法，具有具体结构对算法的适应性好、设计周期短、系统易于优化等特点。 |
| 8. | We use different commercial eda tools in order to achieve better implementation in different design phase , which include silicon ensemble of cadence , design compiler and design primer of synopsys and so on
在设计的不同阶段使用了不同的主流eda工具进行辅助设计和验证，包括synopsys公司的逻辑综合工具designcompiler 、静态时序分析工具designprimer和cadence公司的自动布局布线工具siliconensemble等。 |
| 9. | Then , a new design automation methodology is put forward which uses uml for specification , systmec for simulation and synopsys tools ( cocentric systemc compiler ) for hardware synthesis . the main feature of this methodology is its high possibility of implementation
提出了一个基于uml系统描述的， systemc模拟验证的，利用cocentricsystemccomplier进行硬件综合的自动化设计方案，这个方案最大特点是可实现性强。 |
| 10. | Except for design methodology and technique , some comprehensive experiments are performed . these experiments use some eda tools , including functional simulation with cadence ' s verilog xl , logic synthesis with synopsys ' s design compiler
本文除了介绍的设计方法和设计技巧，还做了一些有益的实验，使用到许多流行的eda工具，如cadence公司的verilog - xl 、 siliconensemble ， synopsys公司的designcompiler 、 physicalcompiler等。 |
