English translation for "芯片级"

onc on chip

Related Translations:

磊芯片:  led epi wafer

晶体管芯片:  transistor chip

芯片处理:  chiprocessingdie processingwafer processing

芯片编号:  chip number

芯片数量:  chicountcount, chip

芯片粘贴:  die bonding

测试芯片:  test chiptest die

微芯片:  microchip

芯片操作系统:  cos chioperation system

性格芯片:  personality chips

Example Sentences:

	1.	As examples of vfg , this paper introduces in detail the system - and chip - level vfg of electronic devices 作为虚拟特征生成实例，本文以电子设备概念设计为例，详细介绍了系统级和芯片级的虚拟特征生成方法。
	2.	Description of some of the expected future developments in time and frequency standards and distribution , including such topics as chip - scale atomic clocks ( size of a rice grain , powered by aa battery , potentially capable of low cost mass production ) 介绍一些未来可预期的时间频率标准和发布技术的进展，包括诸如“芯片级的原子钟” （大米粒尺寸，由aa电池供电，具有低成本大批量生产潜力） 。
	3.	For the training of professional system , the identification of suppliers , and the practical project , sv has the professional project engineers advanced in the av technique in china , who can offer blue print of design , installation , training and the maintenance of chip level 专业系统的培训与厂商认证及丰富的实际工程经验,索讯拥有国内最早从事av技术的工程技术人员，能够为客户提供方案设计、安装、培训与芯片级维修
	4.	The " chip _ level " fault detection was implemented by means of diagnosing technology and experimental methods . the experimental results indicate that this system is fast , accurate , ease to use , portable and applicable for practicable use 通过软件、硬件技术的结合，采用多种检测技术及实验方法，达到了芯片级故障定位的设计目的。实验结果表明，本系统具有故障定位准确、检测速度快、操作简便和便携式等特点，具有较高的实用价值。
	5.	Similar with design verification problem , to predigest chip level layout synthesis problem , the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells . however , along with the increasing of chip size , chip level layout synthesis problem become more complex if it still bases on general manual standard - cell . because the router cannot impose the characteristic of the transistors in the standard - cell , it may reduce the performance of the whole chip 通常，基于标准单元布图模式将版图综合划分成单元内与单元间两个层次，以简化芯片级自动版图综合问题的复杂性；但随着芯片规模的不断扩大，基于主要以手工定制的小规模标准单元，芯片级版图综合问题的复杂性不断增大，且标准单元间布线无法充分利用单元内晶体管特征，影响芯片的整体性能。

Similar Words：

"芯片互连" English translation, "芯片缓存器结构" English translation, "芯片激活" English translation, "芯片激活输入" English translation, "芯片集" English translation, "芯片级多处理" English translation, "芯片级封装" English translation, "芯片级封装技术" English translation, "芯片级封装芯片级安装" English translation, "芯片级集成" English translation