English translation for "解码电路"
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- decoding circuit
demoding circuit
Related Translations:
解码作业: decode operationdecoded operation 序列解码: sequential decoding 解码矩阵: decoder matrixdecoding matrix
- Example Sentences:
| 1. | The parallel form of the input sequence is decoded by means of a logical decoding circuit .
此并行形式序列通过逻辑解码电路输入。 | | 2. | Colour decoding circuit
彩色解码电路 | | 3. | 2 . quick check and verify for address decoding or data transceiver circuits , which designed
2 .可快速验证cv - 16解码电路之8bit或16bit资料读写值是否正确 | | 4. | After being hdl simulated and fpga verified , the itu656 decoder worked in decoding function
经hdl仿真及fpga验证, itu656解码电路实现了数据解码的功能。 | | 5. | By systemview , hdl simulation and fpga verification , the results showed that the decoder met commercial ic requirements
经systemview , hdl仿真及fpga验证,结果表明:所设计的数字视频解码电路的各项性能达到了芯片商用要求。 | | 6. | According to theories of television and the video format of itu601 and itu656 , the itu656 decoder and digital video decoder were designed
依据电视技术的基本原理及itu601 、 itu656标准的视频格式,完成了itu656解码电路和数字视频解码电路的设计。 | | 7. | The chapter of hardware design first expounds the whole design . the several primary circuit are designed , including power circuit , controlling circuit , detecting circuit and the dsp quadrature encode circuit
硬件部分先作了整体设计的论述，然后具体介绍了功率电路、控制电路、检测电路以及dsp的正交解码电路。 | | 8. | The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3 . 2k internal fifo cache embedded , at the scale of 46k gates . its encoding and decoding speed are 66mhz and 47mhz respectively
布局布线后结果表明本文所设计的rs编码器的速度可达到66mhz ；解码速度可达到47mhz ，电路规模为4 . 6万门，包含有3 . 2k的内部缓存fifo的rs编/解码电路。 | | 9. | The results of the hdl simulation and fpga verification showed that image enhancement improved greatly the image quality . cooperating with software a circuit that can read and write flash memory and a remote controller hardware decoder were also designed in this thesis . after hdl
本文还设计了与软件配合能读、写闪存的电路以及红外遥控的硬件解码电路,经hdl仿真及fpga验证,所设计的两种电路能完全满足芯片商用要求。 | | 10. | The control system included the following units : video decode unit , data format conversion unit , fpga controller , cache unit and d / a monitor . the above self - design control unit plus row and column power supply units make the whole fed driving system , thus drove the 25 inch sample and realized color video display . the 25 inch vga sample thus fabricated could display video images , and obtained its brightness 400cd / m2 , contrast ratio 1000 : 1 , 256 circuit gray scale
本文介绍了fed驱动系统的工作原理,重点论述了基于fpga的vga级彩色fed新型驱动控制系统的研制,这种新型fed驱动控制系统主要包括视频解码电路、数据格式转换电路、 fpga控制电路、数据缓存电路和d / a监控电路,配合后级列灰度调制单元和行扫描单元,组成完整的fed驱动系统,可以驱动25英寸vga级fed显示屏,实现彩色视频显示,样机亮度达400cd / m2 、对比度为1000 : 1 ,灰度等级为256级。 |
- Similar Words：
- "解码成了" English translation, "解码程序" English translation, "解码触发脉冲" English translation, "解码达文西" English translation, "解码单元" English translation, "解码定标" English translation, "解码方案" English translation, "解码过程" English translation, "解码盒" English translation, "解码机" English translation
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