| 1. | ( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis "
( 4 )设计并实现了“多级逻辑综合延迟均衡”算法。 |
| 2. | 2 . the logic synthesis process is studied in detail and the relative constraints are discussed
2 .详细研究了soc应用设计流程中的逻辑综合技术方法。 |
| 3. | Product shrinkage , general sum shrinkage , elimination and extraction operators are proposed to shrink the truth vector
但是， rm逻辑综合和优化是困难的,尤其是对混合极性的rm逻辑，则更是这样。 |
| 4. | Finally , their applications in the logic synthesis based on the partial linear function and calculating boolean difference of logical functions are discussed
最后讨论了它们在逻辑综合以及计算逻辑函数的布尔差分中的应用。 |
| 5. | So the sta ( static timing analysis ) step and the iteration between synthesis and p & r ( place & route ) were integrated in the dsm design flow
因此，需要在深亚微米设计流程中加入静态时序分析环节，以及逻辑综合和布局布线之间的迭代过程。 |
| 6. | Programs with verilog language , which describe all modules of the hardware construction , have been given and succeed in the logic simulation and synthesis
根据该算法的硬件结构，编写了结构中所有的veriloghdl模型，并成功进行了仿真和逻辑综合。 |
| 7. | The digital one includes spec , verilog coding , simulation , synthesis , floorplan , routeing , static timing analyze and drc / lvs check
数字电路设计流程则包括：制定spec ， verilog代码编写，仿真，逻辑综合，布局，布线，静态时序综合和drc lvs检查。 |
| 8. | Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description
逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。 |
| 9. | At last , the paper involves the flow and related data of logic simulation , logic synthesis and test vector in the risc cpu
论文最后给出了64位vegacpu的asic逻辑仿真文件和仿真波形，逻辑综合策略、综合脚本和综合结果，以及vegacpu基于atpg的测试向量设计流程和相关数据。 |
| 10. | In the process of design , simulation is achieved by active hdl , and synthesis is achived by symplify , and finally the chip is downloaded in quickpro
在硬件逻辑设计过程中，借助activehdl进行硬件逻辑前后仿真，使用symplify工具进行逻辑综合，最终在quickworks下生成fpga芯片。 |
