English translation for "除法器"

divider

Related Translations:

除法语句:  divide statement

硬件除法:  hardware division

精确除法:  exact division

除法单元:  divider

综合除法:  synthetic division

除法装置:  devision device

除法检查:  divide check

浮点除法:  floating-point division

除法子程序:  dividing subroutinedivision subroutine

刮除法:  curettagesgraffito

Example Sentences:

	1.	Abstract : this paper introduces a new power factor meter with sample hod circuit and divider and provides basic measurment circuit . experiment result proves the practicality of the power factor meter 文摘:本文介绍了利用采样保持器和除法器实现的功率因数测量仪表，给出了测量电路原理图，实验结果表明了该测量仪表的实用性。
	2.	The number of error symbols that can be corrected by the decoder is 2 . the design process includes storing the input data , calculating the syndromes , designing multiplier and divider and solving the key equation Rs （ 256 ， 252 ）译码器的设计过程主要包括输入数据的存储、伴随式的计算、乘法器和除法器的设计、关键方程的求解等几个步骤。
	3.	Then we show an algorithm design of the elliptic curve crypto based on galois field . as a main part , the design theory and concrete solution of it are presented step by step , ic chip design method for implementation of the algorithm is described in detail 设计完成了一种基于有限域的椭圆曲线加密算法，主要包括适合于168bit椭圆曲线加密的有限域乘法、加法、除法器的实现； 4
	4.	Chapter 5 gives the design illumination of the rs coder and decoder based on fpga . then it gives the integrated results for realization design of the rs ( 31 , 15 ) error - correcting code . after that , it gives the functional and layout simulation results for the limited field multiplier , divider , rs coder and rs de - coder 第五章给出了基于fpga实现的rs编码器和译码器设计说明, rs ( 31 , 15 )纠错码设计实现的综合结果,有限域乘法器、除法器、 rs编码器、 rs译码器的功能仿真和布局布线后仿真结果,最后总结主要的调试经验。
	5.	It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ) , 5 - stage pipeline , hardware multiplier and divider , interrupt controller , 16 - bit i / o port and a flexible memory controller . new modules can easily be added using the on - chip amba ahb / apb buses . it has flexible peripheral interfaces , so can be used as an independent processor in the board - level application or as a core in the asic design 它遵照ieee - 1745 （ sparcv8 ）的结构，针对嵌入式应用具有以下特点：采用分离的指令和数据cache （哈佛结构） ，五级流水，硬件乘法器和除法器，中断控制器， 16位的i / o端口和灵活的内存控制器，具有较强的异常处理功能，新模块可以轻松的通过片上的ambaahb / apb总线添加。

Similar Words：

"除法检验事故" English translation, "除法键至位址变换" English translation, "除法列子程序" English translation, "除法律另有规定外" English translation, "除法滤波器" English translation, "除法器，分割器" English translation, "除法器电路" English translation, "除法器两脚规" English translation, "除法散列" English translation, "除法时间" English translation