Chinese translation for "board-level"

插件板级的

Example Sentences:

	1.	Board - level design for testability based on jtag 的板级可测试性设计
	2.	Application of boundary scan technique to the design for board - level test 边界扫描技术在板级可测性设计中的应用
	3.	To that end , a demonstrable board - level commitment to an effective formal quality management system must exist 为此，公司高层必须为一个有效正式的质量管理体系提供可以证明的承诺。
	4.	Using visual c + + , a board - level test vector generation and fault diagnoses software were designed and carried out 在visualc + +环境下,设计并实现了板级测试矢量生成软件和故障诊断软件。
	5.	The results show that the viscoelasticity of pcb and its size have distinct influence on dynamic properties of pcb under board - level drop impact 结果表明，电路板的黏性系数和尺寸对板的动力学特性有显著影响。
	6.	Otherwise , by using some board - level test theories and methods , a test resolution , including bst infrastructure integrity test , interconnect test and cluster test was given 另外,结合板级测试的相关理论和方法,提出了一套板级测试解决方案,包括扫描链完整性测试、互连测试和簇测试。
	7.	He holds a post - graduate degree in business computing , besides having board - level experience in corporate communications , bid management , business development , corporate finance , and information technology 他拥有商业计算机专业的硕士学位，同时在企业通讯、招标管理、业务发展、公司融资、信息科技等行业均担任过董事职位。
	8.	Indeed , most directors are unaware of the growing body of knowledge that is now available about the work of directors , board - level effectiveness and the exercise of power of the modern corporate entity - what is now called corporate governance 事实上，大部分董事都不知道现时有一门发展迅速、称为公司管治的学科。这门学科专门研究有关董事职务、董事局的工作效率、现代化公司组织的权力运用等。
	9.	Followed above , this dissertation has much content about the hardware design which include dsp , fpga , ddr sdram memory bank interface circuit , pci , power circuit , board - level interconnection design . this part puts much emphasis on key circuits many of which require us to have deeply known the components adopted and involved specifications 这部分主要是对电原理图的重要地方和需要注意的地方进行重点阐述,包括dsp 、 fpga 、 ddrsdram内存条接口电路、 pci接口电路、电源、板级互连等部分。
	10.	Then a comparison is made according to their characters and the application scope of each method is determinate . from that we get the whole scheme of design for testability of dspc50 , which is using boundary scan to improve the board - level testability of the chip and using full - scan in designing the nuclear circuit to reduce the difficulty of testing the chip 在此基础上得到dspc50的可测性设计的整体方案，即采用边缘扫描设计提高芯片在板级的可测性，同时用全扫描思想设计芯片核心电路，以降低芯片本身测试的难度，即将芯片的全扫描设计包含入边缘扫描系统。

Similar Words：

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