| 1. | Grasp the relationship between the parts of division
除法的意义和乘除法的各部分间的关系。 |
| 2. | Hardware multiplier and divider
支持硬件乘除法 |
| 3. | A few seconds of fiddling let scientists and engineers multiply , divide and find square and cube roots
只要拨弄几秒钟，科学家或工程师就能计算乘除、求出平方根与立方根。 |
| 4. | The historical origin of vajrayana is unclear , except that it coincided with the spread of the mentalistic schools of buddhism
金刚乘除了与佛教的灵性学派发展相符之外，它的历史起源并不清楚。 |
| 5. | This additivity is obvious in their reduction of multiplication and division to the same process by breaking up higher multiples into a sum of consecutive duplications
这种加在它们的乘除变形是明显的，通过阻止更高倍数进入一系列连续复制里。 |
| 6. | There were good two hundred seventy - four six - graders from two different elementary schools located in both taichung city and taichung county were selected to do this test
研究工具为自编乘除拟题能力测验，施测后分析学生所拟出之数学题目的拟题结果、拟题背景、错误类型与后设认知。 |
| 7. | The multi - objective decision problem was transformed to the mono - objective problem by the multiply - divide method , and its constraint functions were transformed to the objective functions by a multiplication penalty function
使用化多为一的乘除法，将该多目标决策问题转化为单目标问题求解，提出了使用乘法形式的罚函数将模型中的约束函数转化为目标函数。 |
| 8. | Listen to the inventor : “ cast away from the work itself even the very numbers themselves that are to be multiplied , divided , and resolved into roots , and putteth other numbers in their place which perform much as they can do , only by addition and subtraction , division by two or division by three
听听发明人是怎麽说的：免除繁杂的手续，甚至抛开要用来乘除和开方根的数字本身，用其他具备相同功能的数字取代，但将计算改成加减、除以2和除以3 。 |
| 9. | In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future
第五章提出了基于ieee754浮点标准的浮点运算处理器的设计和异步串行通信核的设一浙江大学博士学位论文计，提出了适合硬件实现的浮点乘除法、加减运算的结构，浮点运算处理器主要用于高速fft浮点处理功能，异步串行通信核主要用于pft处理器ip核的外围扩展模块以及本文所做的验证测试平台中的数据接口部分第六章提出了面向系统级芯片的可测试性设计包括了基于扫描测试atpg 、内建自测试bist 、边界扫描测试jtag设计，在讨论可测试性设计策略选择的问题上，提出了针对不同模块进行的分别测试策略，提出了层次化jtag测试方法和扫描总线法，提出了基于fpga |
| 10. | Then the thesis presents two peephole optimizations for the c 、 c + + compiler based on the architecture of thump to improve the quality of generated codes . one optimization is on multimedia applications . since thump supports two mmx instructions , the optimized compiler can generate these instructions to improve the performance
论文讨论了如何利用thump体系结构的特点进一步提高目标代码生成质量的优化技术，并实现了两种窥孔优化，包括针对thump的多媒体指令的优化算法和基于thump的高速乘除处理部件的优化算法。 |
