| 1. | Design of high - frequency local source of very small aperture terminal
高频锁相环的可测性设计 |
| 2. | Application and analysis of the scan path in asic ' s testable design
可测性设计中扫描路径的应用与分析 |
| 3. | Dft for high - frequency pll
高频锁相环的可测性设计 |
| 4. | Application of boundary scan technique to the design for board - level test
边界扫描技术在板级可测性设计中的应用 |
| 5. | Design for testability means adjusting the structure of circuit and making the circuit easy to test
可测性设计即调整电路的内部结构，使电路变得易测。 |
| 6. | By using design for testability , we can abridge the contriving period and reduce the cost
对电路进行可测性设计，将缩短产品的开发周期、降低产品的开发成本。 |
| 7. | A plan of design for test based of boundary scan testing is introduced for this signal processing system
接着，提出了该信号处理系统基于边界扫描的可测性设计方案。 |
| 8. | This paper presents an effective design ? for ? testability and test scheme for ( fft ) processor
针对快速傅里叶变换处理器，本文提出了一种有效的可测性设计及其测试方案。 |
| 9. | The subject of this dissertation is the research on the design for testability in the design environment of system on a chip
本论文的研究课题为片上系统（ systemonachip ，简称soc ）环境下的可测性设计方法学研究。 |
| 10. | In order to allay the difficulty of test , one should pay attention to the design for testing ( i . e . dft ) during the period of system design
为了减少测试的困难，人们普遍接受的途径是在设计过程中注意到电路的可测性，即所谓可测性设计。 |
