Chinese translation for "可测试性设计"

design for testability

Example Sentences:

	1.	Board - level design for testability based on jtag 的板级可测试性设计
	2.	As a standard technique of test and design - for - testability for testing the digital printed circuit board , boundary - scan technique has obtained widespread application in electronic equipment 边界扫描技术是一种标准的数字电路测试及可测试性设计方法,它在工业界得到了广泛的应用。
	3.	Abstract : bounadary - scan technology is being accepted by m ost engineers as a design - for - testability technique and plays an important role in the test and fault diagnosis of electonical devices . in this paper , a boundary - scan prototype tester is introduced 文摘:边界扫描是一种正在被人们普遍接受的可测试性设计技术，在电子设备测试和故障诊断中发挥着越来越重要的作用。
	4.	Not only the scan route solution , the built - in self - test solution and the boundary scan solution of design for testability are summarized , but also the applications and countermeasures of these 3 solutions are analysed and compared in details 摘要综述了超大规模集成电路的几种主要的可测试性设计技术，如扫描路径法、内建自测试法和边界扫描法等，并分析比较了这几种设计技术各自的特点及其应用方法和策略。
	5.	In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future 第五章提出了基于ieee754浮点标准的浮点运算处理器的设计和异步串行通信核的设一浙江大学博士学位论文计，提出了适合硬件实现的浮点乘除法、加减运算的结构，浮点运算处理器主要用于高速fft浮点处理功能，异步串行通信核主要用于pft处理器ip核的外围扩展模块以及本文所做的验证测试平台中的数据接口部分第六章提出了面向系统级芯片的可测试性设计包括了基于扫描测试atpg 、内建自测试bist 、边界扫描测试jtag设计，在讨论可测试性设计策略选择的问题上，提出了针对不同模块进行的分别测试策略，提出了层次化jtag测试方法和扫描总线法，提出了基于fpga
	6.	With the high development of the quantum circuits , the testability of the circuits will become a very serious problem . the method of testability design for rt circuits is proposed in the end of this paper , which has high testability and low hardware cost . only adding one extra mos transistor and two control ports , it can detect all open and short faults in rt circuits 随着量子电路的飞速发展，由于其本身所特有的高集成度特点，电路的测试必然会成为越来越严重的问题，因此论文在最后就电路中常见的开路、短路故障提出了rt电路的可测试性设计方法，并针对具体的mobile电路进行了可测试性设计， pspice模拟结果表明达到了可测试的目的。
	7.	Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip , the construction and application of asip is also analyzed . the fourth chapter introduces the design flow using eda tools based on standard cell , then it presents the dft of this chip in detail which uses following techniques : full scan , bist and boundary scan to improve the fault coverage 第四章，在对本芯片的基于标准单元eda设计流程进行了简要说明基础上，对本芯片采用的可测试性设计进行了详细的分析和说明，本芯片中有机结合了多种可测试性设计技术：基于全扫描的方式、 bist测试技术、边界扫描技术，保证了很高的测试故障覆盖率。
	8.	Certainly ic design involves many aspects , this paper only covers the theory , algorithm , architecture and design philosophy of the chip . it starts from the analysis of the theory and algorithm , then it presents the system architecture and some strategies used to realize chip hardware / software co - design , moreover this paper analyzes the design for testability ( dft ) of the chip , finally goes deep into the study of the verification method and its role in the whole design flow of the chip 芯片设计涉及的内容是很广泛的，但本文主要从该芯片算法原理、实现结构和设计方法等方面进行分析和研究：从信道接收芯片各个主要模块的原理和算法分析入手，提出系统的实现结构和采用软硬件协同设计的策略，然后对芯片可测试性设计进行了分析，最后对整个芯片设计的验证策略做了深入的研究。
	9.	This work puts forward different kinds of testing methods for different models of the charge pump phase - locked loop and strongly describes how to combine the various tests into a unified strategy - all - digital dft ( design - for - test ) testing analysis for charge pump phase - locked loop 摘要以电荷泵锁相环为对象，提出了针对电荷泵锁相环各个模块的不同测试方法，著重论述了如何在一个完整的测试方案中把不同的测试方法结合起来即采用电荷泵锁相环的全数字可测试性设计( dft )法。
	10.	Test ' s methods change and inprovement continuously , automatic test is becoming main method in electronics products " test . at the situation , my institute wants to develop general - purposed automatic test equipment , which is used for testing our embedded computer products , this dissertation is discuss about this research item , the main contributions in this dissertation are given below . by analyzing the testabilitily of a embedded computer system with the testability design rules in engineering practice , we ' ve completed total test schema of the computer system 在此背景下，我单位(中国航空计算技术研究所)开展了通用自动测试设备的研制及开发工作，用于对我所在单位的嵌入式计算机产品的验收和维修测试，本论文围绕这项工作展开，所做的主要工作及论文内容如下：通过面向嵌入式系统可测试性分析，针对嵌入式系统的特征和可测试性要求，结合工程中可测试性的设计原则，对某机载嵌入式计算机的可测试性设计进行分析，在此基础上，完成了产品测试的总体方案。

Similar Words：

"可测事件" Chinese translation, "可测试故障" Chinese translation, "可测试性" Chinese translation, "可测试性程式" Chinese translation, "可测试性分析" Chinese translation, "可测随机过程" Chinese translation, "可测特性" Chinese translation, "可测推力" Chinese translation, "可测温度" Chinese translation, "可测温升" Chinese translation