| 1. | The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究内容正是面向非扫描同步时序电路的并行atpg算法。 |
| 2. | Optimize synchronous sequential circuit with retiming was introduced by leiserson and saxe in 1983 , and retiming optimizational algorithm was summarized comprehensively in 1991
Leiserson和saxe于1983年提出了利用重定时优化同步时序电路，并于1991年对重定时优化算法做了全面的总结。 |
| 3. | Based on a sequential word - level fault parallel fs algorithm , we develop a multi - processor fault parallel fs algorithin and a multi - processor pattern parallel fs algorithin
并设计了针对同步时序电路的基于单机字级故障并行fs算法的多机故障并行fs算法和基于确定性算法的多机测试码并行fs算法。 |
| 4. | ( 2 ) retiming , which can optimize the rapidity , area and functional extravagance through moving the sequential elements and change the number of sequential elements
( 2 )重定时，重定时在保证功能不变的前提下，通过移动时序元件的位置和改变时序元件的个数来优化同步时序电路的速度、面积和功耗。 |
| 5. | In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits , the algorithms of retiming is deeply researched in this paper
本文对重定时算法进行了深入研究，目的在于消除同步时序电路的时序冲突，从而缩短集成电路的设计时间。 |
| 6. | Base on the existing synchronous sequential circuits fault simulator - hope , the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly
本文在同步时序电路故障模拟器? hope的基础上，率先对基于蚂蚁算法的时序电路测试矢量生成方法作了系统的开拓性研究。 |
| 7. | As emphasis , we propose a new backward width - flrst search circuit partitioning method with flip - flop as core for synchronous sequential circuits . and then based on it , we develop a new circuit parallel tg algorithm
最后重点对电路并行方法进行了研究，提出了一种新的以触发器为核且消除大功能块之间反馈的宽度优先反向搜索同步时序电路划分方法。 |
| 8. | For examp1e , the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion
其中，编排级数法确定了组合逻辑的层次关系；通路敏化输入波形方法决定了最小时钟周期；基于周期的同步时序电路的仿真算法加快了仿真的速度等。 |
| 9. | Test vector generation based on ant algorithm is presented and implemented , the pheromone computation formula for sequential circuits and status transfer rules are given , and the test results are compared with the results of the other existing test generators - hitec , gatest , cris , digate and strategate , based on standard sequential circuits iscas ' 89 and other synchronous sequential circuits
提出并实现了基于蚂蚁算法的测试矢量生成，给出了针对时序电路测试矢量生成的信息素计算公式和状态转移规则。在iscas ’ 89标准时序电路和几个同步时序电路上实现了测试生成，并将生成结果和其它现有测试生成器( hitec ， gatest ， cris ， digate ， strategate )的生成结果作了比较、分析。 |
| 10. | We first propose and implement a sequential word - level pattern parallel fs algorithrn for synchionous sequential circuits . differing from other similar algorithins , it utilizes the relative independence of every fault test sequence generated by the g - f two - value tg algorithm , pwtitions and dynamically mounts test pattem , avoids redundant simulation for added synchlronous sequence , and gets better results
首先提出并实现了一个新的同步时序电路单机字级测试码并行fs算法，该算法与现有同类方法的不同在于，利用确定性g - f二值tg算法的每个故障测试序列之间的相对独立性，对测试码进行分解并动态组装，避免了对添加的同步序列的冗余模拟，效果较好。 |
