| 1. | Vdsm ulsi place and route optimization research
布局布线优化设计研究 |
| 2. | After succeeding in post - synthesis simulation , i place & route the protocol processor by xilinx ’ s integrated software ise
综合后仿真通过后,采用xilinx公司的集成软件ise对协议处理器进行布局布线。 |
| 3. | Then the standard delay file is back - annotated into post - place & route simulation module to do the post - place & route simulation
布局布线后,将标准延时文件反标注到后仿真模型上,对设计进行布局布线后仿真。 |
| 4. | After these , the usb host controller was simulated , synthesized and placed and layout by activehdl , synplify and quartus ii
并分别以activehdl 、 synplify ，和quartus完成了usb主控制器的前后仿真、综合与布局布线。 |
| 5. | With all the methods above , a wonderful floorplan with good placement and high routebility and low power and timing convergence has been achieved
运用上述理论,本文完成了一款750万门数字soc电路自动布局布线,并预计7月份流片试验。 |
| 6. | It has also completed asic implementation of pci target controller . and it summarizes synthesis and placing & routing of asic design technique
并且在此基础上完成了pci目标设备控制器的asic实现，总结了asic设计的综合和布局布线方法。 |
| 7. | The thesis proposed a new back - end design method , which is a design flow combines physical compiler and silicon ensemble effectively
文中提出了一种后端设计的新方法，即physicalcompiler综合和siliconensemble布局布线有效结合的设计流程。 |
| 8. | So the sta ( static timing analysis ) step and the iteration between synthesis and p & r ( place & route ) were integrated in the dsm design flow
因此，需要在深亚微米设计流程中加入静态时序分析环节，以及逻辑综合和布局布线之间的迭代过程。 |
| 9. | This tool can compress the verilog code by more than a factor of 5 , increase the efficiency of the front - end design and reduce the bug rate significantly
这些工具对提高编码的效率和质量很有帮助。高质量的代码不仅可以减小验证的工作量和压力，也为后端布局布线的工作提供了便利。 |
| 10. | Some anti - interference techniques are introduced such as appropriate circuit layout and wiring , the component and device screening as well as digital filter and the zero point processing in software
提出了通过从电路合理的布局布线和元器件的筛选以及软件的数字滤波和零点处理等措施来达到抗干扰的目的。 |
