Chinese translation for "扫描链"

scan chain

Example Sentences:

	1.	Yu hu , yinhe han , huawei li , tao lv , and xiaowei li , " pair balance - based test scheduling for socs " ， in : proc . of ieee asian test symposium ( ats ) , nov . 2004 , pp . 236 - 241 董婕，胡瑜，韩银和，李晓维， "基于组合解压缩电路的多扫描链测试方法" ，计算机研究与发展，已录用。
	2.	Otherwise , by using some board - level test theories and methods , a test resolution , including bst infrastructure integrity test , interconnect test and cluster test was given 另外,结合板级测试的相关理论和方法,提出了一套板级测试解决方案,包括扫描链完整性测试、互连测试和簇测试。
	3.	Based on the addition algorithm , the design was optimized by the method of scan chain control and iterative invoke and realized 14 kinds of large - number operations such as addition , subtraction , multiplication , division , module addition , module multiplication , module exponential , etc 基于简单的加法操作，采用扫描链控制、迭代调用等方法对设计进行优化，实现了14种基本的大数运算功能。
	4.	First , the low testing power dft solution - - scan array architecture are presented . in the scan array , the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode 首先，从优化测试功耗的角度出发提出了扫描阵列结构，通过加入wrapper测试控制结构以及构建并行化的分支扫描链，有效地将测试功耗降低到与正常工作功耗相当的量级。
	5.	Chapter two detailedly presents the design of the boundary scan testing system which is in accordance with ieee . 1149 . correspondingly two special - used data registers are added , one of which is the scanning chain register and the other is the child scanning chain control - register 文中第二章按照ieee . 1149标准详细设计了边缘扫描测试系统，相应增加了两个专用数据寄存器，其中一个为扫描链寄存器，一个为扫描子链控制寄存器。
	6.	During test , some registers in the processor are converted into scan chains to improve controllability of the circuit , the adders in the processor are used as test generators , and the produced test patterns can detect any combinational faults within every basic building cell of fft processor 测试时，该方案将处理器中的寄存器作为扫描链提高了其可控性，利用其中的加法器作为测试生成，生成的测试矢量能侦测处理器每个基本组成单元内部的任意组合失效。
	7.	After that , it introduces the design for test techlonogy in this chip and some valuable and important methods of debugging and testing for both the chip and fpga systems . the main contributions of this paper are discussing the core algorithms in post - process chip and their implementations in asic . it also proposes some constructive ideas of the debugging and testing of the asic and fpga systems 另外，在芯片的可测试性方面，创造性地提出了利用芯片内部的扫描链进行功能故障测试的思想；在fpga系统的调试方面，创造性地提出来利用计算机并口的epp模式构建测试平台的思想，同时把这两种思想成功运用于芯片测试和验证中。

Similar Words：

"扫描类型" Chinese translation, "扫描棱镜" Chinese translation, "扫描离子微区探针" Chinese translation, "扫描离子显微镜" Chinese translation, "扫描立体镜" Chinese translation, "扫描量程" Chinese translation, "扫描量热法" Chinese translation, "扫描量热仪" Chinese translation, "扫描亮度" Chinese translation, "扫描亮度增强" Chinese translation