| 1. | A microprocessor designer may decide to make all instructions last five clock pulses .
微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。 |
| 2. | The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。 |
| 3. | Number of timing phase
时钟脉冲相数 |
| 4. | Clock pulse circuit
时钟脉冲电路 |
| 5. | Clock pulse width
时钟脉冲宽度 |
| 6. | The counter output , which represents a binary number , decreases by 1 any time the counter is triggered by a pulse
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1 。 |
| 7. | Combined with the orcad pspice software , it also simulates the clock pulse circuits and relay circuits on the motherboard . the simulation results can satisfy the requirement of the circuit design
并对母板上的时钟脉冲电路、继电器电路应用orcadpspice进行了模拟仿真，仿真结果符合电路设计要求。 |
| 8. | If the host pulls clock low before the first high - to - low clock transition , or after the falling edge of the last clock pulse , the keyboard / mouse does not need to retransmit any data
如果在第一个高- >低时钟跳变时， （或者在最后一个时钟脉冲的下降沿之后）主机将时钟拉低，键盘/鼠标不必重新传输任何数据。 |
| 9. | One of the most promising new technologies to help achieve that goal is a new breed of low - powered microprocessors that can vary the speeds at which they operate
在执行复杂的计算任务，如连续处理大批的数字数据时，这种处理器以极高的速度，即"时钟脉冲速度"运行。但是在执行要求较低的任务，如运行一个文字处理器或放音乐时，该芯片能减速。 |
| 10. | The current models have phased out the g3 but continue to use the similar g4 , both 32 - bit chips , running at various clock speeds ; the recently introduced g5 is a 64 - bit ibm chip that mostly adds some multimedia - specialized instructions to the power4 chip models
当前的g3型已经逐步被淘汰，取而代之的是类似的g4型，它们都是32位芯片，运行于不同的时钟脉冲速度下；最近推出的g5是一款64位ibm芯片，主要是向power4型芯片中添加了一些多媒体专用指令。 |
