| 1. | Familiar with deep submicron process design rule
熟悉深亚微米工艺设计规则。 |
| 2. | Interconnect wire delay questions in deep submicron ic design
深亚微米集成电路设计中的互连线延迟问题 |
| 3. | Numerical simulation of air sliders in an ultra sub - micron flying system
深亚微米飞行系统滑块的数值仿真 |
| 4. | Longer paths tend to be sensitive to crosstalk - induced delay effects because of their short slack time
因此，超深亚微米工艺下，在设计验证、测试阶段需要对串扰问题给予认真对待。 |
| 5. | The main contents of this thesis are at a glance : chapter 1 serves as an introduction to the subject
主要内容如下：第一章简要介绍了atsc - vsb地面广播系统及深亚微米下的eda设计方法。 |
| 6. | The research of this thesis proceeds on two sides : the standardization of ip design and dsm design technique
本论文的研究工作主要从两个方面入手： ip设计的标准化和深亚微米设计技术。 |
| 7. | With the coming of vlsfs sub - micron era , low - power technique has been a growing demand in vlsi design
随着集成电路进入深亚微米时代，功耗问题已成为超大规模集成电路设计考虑的重要因素。 |
| 8. | A resistance macromodel for deep - submicron process epi - type substrate based on the 2d device simulation is presented
摘要提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型。 |
| 9. | This thesis mainly addresses the design of 8 - bit cisc soft ip - 08c01 , based on dsm technology
本论文的主要工作是以8位微处理器软ip ? 08c01为载体，对基于深亚微米工艺的ip设计技术进行研究。 |
