| 1. | Digital lock - in amplifier based on dsp and sampling adc
的数字锁定放大器 |
| 2. | The digital pll is of great importance in the control of the whole system
第三章分析了调制器中所用到的数字锁相环。 |
| 3. | Digital phase - locked loop
数字锁相环 |
| 4. | Design and realization of a single - chip digital phase - locking frequency - multiplier circuit
单片数字锁相倍频电路的设计与实现 |
| 5. | Num lock key
数字锁定键 |
| 6. | Based on the theory of dpll , line phase locked and color subcarrier regeneration were designed
依据数字锁相环的基本原理,完成了行锁相、色副载波还原电路的设计。 |
| 7. | On the numeric keypad with number lock on . you have created three values for the resource named
若要插入带锐音符（如）的字母，请在打开数字锁定的同时使用数字键盘键入 |
| 8. | Research of adaptive spatio - temporal dfe with embedded dpll in high - speed underwater digital communication
内嵌数字锁相环的自适应空时联合均衡器在水下高速数字通信中的应用研究 |
| 9. | Digital phase lock loop is used in this section to synchronize to an incoming serial data stream
数据接收解码模块中使用了数字锁相环技术从输入数据码流中提取出同步时钟信号。 |
| 10. | The digital phase - locked loop designed by isp , which is adapted to optical grating readout is briefly introduced
用isp设计的适合于光栅检测装置的数字锁相环在第七章作了简要的介绍。 |
