| 1. | The digital pll is of great importance in the control of the whole system
第三章分析了调制器中所用到的数字锁相环。 |
| 2. | Digital phase - locked loop
数字锁相环 |
| 3. | Based on the theory of dpll , line phase locked and color subcarrier regeneration were designed
依据数字锁相环的基本原理,完成了行锁相、色副载波还原电路的设计。 |
| 4. | Research of adaptive spatio - temporal dfe with embedded dpll in high - speed underwater digital communication
内嵌数字锁相环的自适应空时联合均衡器在水下高速数字通信中的应用研究 |
| 5. | Digital phase lock loop is used in this section to synchronize to an incoming serial data stream
数据接收解码模块中使用了数字锁相环技术从输入数据码流中提取出同步时钟信号。 |
| 6. | The digital phase - locked loop designed by isp , which is adapted to optical grating readout is briefly introduced
用isp设计的适合于光栅检测装置的数字锁相环在第七章作了简要的介绍。 |
| 7. | 3 . the dpll completed in software was advanced based on comparing the merits and disadvantages of analog pll with that of dpll . 4
比较了模拟锁相环和数字式锁相环的优缺点，研究了一种基于软件实现的数字锁相环控制策略。 |
| 8. | The simulation results show the method can attain our aim under harmonic condition . then the calculation errors have been analyzed
仿真结果表明，在有谐波干扰的情况下，数字锁相环方法可以准确地跟踪信号频率的变化和计算相位差。 |
| 9. | Secondly the theory of phased - locked loop ( pll ) is analyzed in detail , and then a method of implementing digital phased - locked loop ( dpll ) is put forward . the algorithm is well implemented using digital signal processor ( dsp )
然后对锁相环原理进行了详细的分析，提出一种数字锁相环( dpll )的实现方法，并采用数字信号处理器( dsp )加以实现。 |
| 10. | In this paper , we are going to use high speed digital signal processor , track the carrier wave through the digital phase locked loop , and so to demodulate the modulating signal . it can overcome the difficult problems of the other ways
而我们这里就是准备用高速数字信号处理器，利用数字锁相环实现对载波的跟踪，从而实现调制信号的解调，它能有效克服其他解调方式所遇到的困难。 |
